Pixel clock is 25.125 MHz. // Timing estimate: 41.33 ns (24.20 MHz) So close, but not close enough. Looks like my XC7 design won't work cleanly on iCE40 without some extra love. #FPGA

I imagine you've already trimmed the porches as much as you can, but if not, would dropping one or two pixels per line help hit it?

There's some straightforward pipelining I can implement before having to resort to going out of spec on the video signal.

With that close, it will very likely work.

Alas there are some minor graphical artifacts. Plus I need some headroom: a similar design with 8 sprites doesn't reach 20 MHz. Thankfully there's plenty of scope for improvement.

The big issue was ROM not being inferred in BRAM. With XC7 you don't need write enable etc. to infer BRAM. With the ROM fixed the larger font example improved rather dramatically: ROM in logic: 50.85 ns (19.66 MHz) ROM in BRAM: 26.07 ns (38.35 MHz) Much to learn with iCE40. 🙃