Pixel clock is 25.125 MHz.
// Timing estimate: 41.33 ns (24.20 MHz)
So close, but not close enough. Looks like my XC7 design won't work cleanly on iCE40 without some extra love. #FPGA
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I imagine you've already trimmed the porches as much as you can, but if not, would dropping one or two pixels per line help hit it?
Jun 4, 2020 ยท 4:55 PM UTC
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